Cypress S6J3200 Series, Manual

Page: 295 / 1355

CHAPTER 15:12-/10-/8-bit Analog to Digital Converter
294 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
[bit25] TRGCL : Trigger Status Clear bit
Bit Description
0 No effect.
1 Clears corresponding trigger status bits ADC12Bn_CHSTAT0.TRGST and ADC12Bn_TRGST0.TRGST0.
Reading this bit always returns "0".
This bit is identical to the corresponding bit ADC12Bn_TRGCL0.TRGCL0.
[bit24] SWTRG : Software trigger bit
Bit Description
0 No effect.
1
Sets corresponding trigger status bits ADC12Bn_CHSTAT0.TRGST and ADC12Bn_TRGST0.TRGST0.
When trigger status bits are cleared and set at the same time, clearing has priority. When TRGTYP bits are
set to "10" or "11", writing SWTRG bit to "1" has no effect.
Reading this bit always returns "0".
Note:
−
Do not write "1" to this bit and reconfigure TRGTYP with the same access.
[bit23] RCEN : Range Comparator Enable bit
Bit Description
0 Range comparator disabled.
1 Range comparator enabled.
[bit22] RCINVSEL : Range Comparator Inverted Range Selection bit
Bit Description
0
The comparison checks for "outside range", i.e. the over threshold and interrupt flags
(ADC12Bn_RCOTF0.RCOTF0, ADC12Bn_CHSTAT0.RCOTF, ADC12Bn_RCIRQ0.RCIRQ0 and
ADC12Bn_CHSTAT0.RCIRQ) are set when the ADC result is above the upper threshold OR below the
lower threshold. That is called "outside range".
1
The comparison checks for "inside range" i.e., the interrupt flags (ADC12Bn_CHSTAT0.RCIRQ and
ADC12Bn_RCIRQ0.RCIRQ0) are set when the ADC result is below or equal the upper threshold AND
above or equal the lower threshold. That is called "inside range" mode.
[bit21] Reserved : Reserved bit
When writing, always write "0".
When reading, "0" is always read.
[bit20:18] RCSEL[2:0] : Range Comparator Select bit
RCSEL[2:0] Description
000 Select range comparator 0, defined by ADC12Bn_RCOH0 and ADC12Bn_RCOL0 registers.
... ...
111 Select range comparator 7, defined by ADC12Bn_RCOH7 and ADC12Bn_RCOL7 registers.