Cypress S6J3200 Series, Manual

Page: 352 / 1355

CHAPTER 15:12-/10-/8-bit Analog to Digital Converter
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 351
5.22.
Conversion Done DMA Select Registers (ADC12Bn_CDDS0 to 3)
These four registers specify four logical channels whose conversion done interrupt flags can initiate DMA
requests to transfer A/D conversion results to memory. Only ADC12Bn_CDDS0 register is described here.
Other registers (ADC12Bn_CDDS1, ADC12Bn_CDDS2 and ADC12Bn_CDDS3) have identical bit fields.
REGISTER_NAME ADC12Bn_CDDSi (i = 0 to 3)
OFFSET i*2
ACCESS_SIZE B H W
MULTIPLE 0:3
NUMERIC_TYPE
-
OTHER
-
Conversion Done DMA Select Register (ADC12Bn_CDDS0)
BIT_OFFSET 15 14 13 12 11 10 9 8
BIT_NAME Reserved
ACCESS_TYPE R0,W0
PROT_TYPE
INITIAL_VALUE 0x00
BIT_OFFSET 7 6 5 4 3 2 1 0
BIT_NAME Reserved CDCHEN
CDCHNUM[5
]
CDCHNUM[4
]
CDCHNUM[3
]
CDCHNUM[2
]
CDCHNUM[1
]
CDCHNUM[0
]
ACCESS_TYPE R0,W0 R/W R/W R/W R/W R/W R/W R/W
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
[bit15:7] Reserved : Reserved bits
When writing, always write "0".
When reading, "0" is always read.
[bit6] CDCHEN : Channel conversion done DMA dedicated interrupt enable bit
Bit Description
0
Interrupt for triggering DMA request on conversion done interrupt flag (ADC12Bn_CHSTAT0 to
63.CDONEIRQ = ADC12Bn_CDONEIRQ0 to 1.CDONEIRQ = "1") of the logical channel defined by
CDCHNUM bits is disabled.
1
Interrupt for triggering DMA request on conversion done interrupt flag (ADC12Bn_CHSTAT0 to
63.CDONEIRQ = ADC12Bn_CDONEIRQ0 to 1.CDONEIRQ = "1") of the logical channel defined by
CDCHNUM bits is enabled.