CHAPTER 24:Inter-IC Sound (I2S)
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
917
3.3.
Bit Alignment
Transmission Word Alignment
Figure 3-3 Transmission Word Line Chart
When transmission is performed with serial bus, word is sent MSB first when I2Sn_CNTREG:MSLB is "0"
and LSB first when the value is "1". When channel length (set to I2Sn_MCR0REG:S0CHL and
I2Sn_MCR0REG:S1CHL) is longer than the word length (set to I2Sn_MCR0REG:S0WDL and
I2Sn_MCR0REG:S1WDL), remaining bits in the channel become I2Sn_CNTREG:MSKB. Setting the
channel length to shorter than the word length is prohibited.
Notes:
−
AB0, AB1, AB2, AB3, AH0, AH1, and AW on the above chart indicate byte 0, byte 1, byte 2, byte
3, half word 0, half word 1, and word at write accessing to I2Sn_TXFDAT0 to 15 on AHB bus
31 30 29 28 27
25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
6
2
0
26
1
3
4
5
7
8
9
31 30 29 28 27
25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
6
2
0
26
1
3
4
5
7
8
9
AB0
AB3
AH1
AW
AH0
AB2
AB1
FB2
FH2
LSB
FB1
FB3
FH1
FW
FB0
Image of I2Sn_TXFDAT0~15 written to FIFO
Image of CPU written to I2Sn_TXFDAT0~15 register
The data written to I2Sn_TXFDAT0~15 register from CPU or DMA is written to transmission FIFO after right justified
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
LSB
MSB
MSB
LSB
MSB
LSB
MSB
LSB
LSB
MSB
LSB
LSB
MSB
MSB
MSB
FH1
FH0
Summary of Contents for S6J3200 Series
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