Cypress S6J3200 Series, Manual

Page: 1019 / 1355

CHAPTER 27:HyperBus Interface
1018 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
[bit26] WRSTOERR : RSTO Error in Write Transaction
This bit indicates whether HyperBus memory is under reset state in the latest write transaction.
Bit Description
0 Normal operation
1 HyperBus memory is under reset (AXI SLVERR occurs)
[bit25] WTRSERR : Transaction Error in Write Transaction
This bit indicates whether AXI protocol is acceptable by HYPERBUSI module in the latest write
transaction.
Bit Description
0 Normal operation
1 Protocol is not supported (AXI SLVERR occurs)
[bit24] WDECERR : Decode Error in Write Transaction
This bit indicates whether access address is acceptable in the latest write transaction.
Bit Description
0 Normal operation
1 Access address is not reachable (AXI DECERR occurs)
[bit16] WACT : Write Transaction Active
This bit indicates whether write transaction is in progress.
Bit Description
0 Write transaction is idle
1 Write transaction is active
[bit11] RDSSTALL : RDS Stall Error in Read Transaction
This bit indicates whether read data error occurs in the latest read transaction.
Bit Description
0 Normal operation
1 Detect read data error (AXI SLVERR occurs)
[bit10] RRSTOERR : RSTO Error in Read Transaction
This bit indicates whether HyperBus memory is under reset state in the latest read transaction.
Bit Description
0 Normal operation
1 HyperBus memory is under reset (AXI SLVERR occurs)