Cypress S6J3200 Series, Manual

Page: 1195 / 1355

CHAPTER 33:Graphics Subsystem
1194 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
3.1.3.
Capture Clock Measurement
In case the generated display clock should match as close as possible with the input capture clock a clock
measurement utility can be used.
The capture clock must be running before the clock measurement is started for the measurement to work.
Follow these steps to determine the best possible divider:
1. Write 1 to the dsp0/1_MeasurementStart register field to start the measurement.
2. Poll dsp0/1_MeasurementReady until it is 1 again.
3. Check that both dsp0/1_MeasurementNoCapClkError and dsp0/1_MeasurementSlowCapClkError are
0.
4. Read the measurement result from dsp0/1_MeasurementResult.
5. In case the 2D Graphics Core DisEngCfg ClockCtrl setting is set to DIV2 add 1/256 to the read 9.8
fixed point value and divide it by two (halved with rounding).
6. Use the obtained value to setup the display clock generation.
In case the two error fields are not both 0 check that the capture clock is running and that it has a
frequency at which display clock generation is possible.
A restriction applies when using a spread spectrum reference clock. The error_constant can be taken
from the following table:
Table 33-4 Error Constants Values
Center Spread Down Spread
Sinus modulation
4096 2048
Saw tooth modulation 8192 4096
The amplitude is the amplitude of spread spectrum modulation given in percent of clock frequency.
The sscg_frequency is the frequency of the spread spectrum modulation. The following formula must hold
so that the capture clock measurement unit can be used with small enough error: (amplitude *
capture_clock_frequency) / (error_constant * sscg_frequency) <= 0.01.
If the capture clock itself is modulated, the capture clock measurement must not be used.
 Display Clock Generation and Reset Control
The display clock generation can create the display clock from the input reference clock by application of
a fixed point divider. To determine the best possible display clock frequency either use the clock
measurement unit or divide the reference clock frequency by a multiple of 2 of the desired display clock
frequency (if the 2D Graphics Core DisEngCfg ClockCtrl setting is set to DIV2) or directly by the desired
display clock frequency (in case the 2D Graphics Core DisEngCfg ClockCtrl setting is set to DIV1), round
this value to a fixed point with 8 decimal
places and program the result to register field dsp?_ClockDivider. Then set register field
dsp0/1_ClockEnable
to 1 to start generation of the display clock.