Cypress S6J3200 Series, Manual

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CHAPTER 22:Media Local Bus Interface (MediaLB)
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 867
In DMA Mode, system software should set this bit when all the registers, data and program memory
variables are setup and ready to transmit or receive data in DMA Mode.
For transmitting data, the system memory buffer should also be filled. For DMA Mode using ping-pong
buffering, hardware clears this bit after the buffer begins to be processed.
In DMA Mode using circular buffering, the software should clear this bit only when buffer processing
needs to halted.
[bit15:12] STS : STS[15-12] Reserved
Read value is "0". Write always "0" to these bits.
[bit11] STS : STS[11]
This bit has a different interpretation depending on DMA-mode or IO-mode.
In DMA mode this is the Previous Buffer Start bit. When set, this bit indicates the first quadlet of the
Previous Buffer has been successfully transmitted or received. The setting of this bit generates a
maskable channel interrupt to system software. This bit is valid for all channel types.
Write "1" to clear this bit. Writing "0" has no effect.
Once set, this bit holds until it is cleared by software.
In IO Mode, this bit is not used.
[bit10] STS : STS[10]
This bit has a different interpretation depending on DMA-mode or IO-mode.
In DMA mode this is the Previous Buffer Done bit. When set, this bit indicates the last quadlet of the
Previous Buffer has been successfully transmitted or received. The setting of this bit generates a
maskable channel interrupt to system software. This bit is valid for all channel types.
Write "1" to clear this bit. Writing "0" has no effect.
Once set, this bit holds until it is cleared by software.
In IO Mode, this bit is not used.
[bit9] STS : STS[9]
This bit has different interpretation depending on DMA-mode or IO-mode.
In DMA mode this is the Previous Buffer Detect Break bit. When set, this bit indicates that either a
transmit channel has detected a receiver break response, ReceiverBreak (0x70), or a receive channel
has detected a transmitter break command, ControlBreak (0x36) or AsyncBreak (0x26), while processing
the Previous Buffer.
The setting of this bit generates a maskable channel interrupt to system software. This bit is valid for all
channel types.
Write "1" to clear this bit. Writing "0" has no effect.
Once set, this bit holds until it is cleared by software.
In IO Mode this is Receive Packet Start bit. When set, this bit indicates that an RX channel has detected a
transmitter packet start command; ControlStart (0x30) or AsyncStart (0x20). This status bit can be used
by system software to detect when it has reached the end of an aborted packet. This bit is valid for
asynchronous and control RX channels only.