Cypress S6J3200 Series, Manual

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CHAPTER 15:12-/10-/8-bit Analog to Digital Converter
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 341
5.18.2.
A/D Channel Trigger Clear Register (ADC12Bn_TRGCL1)
BIT_OFFSET 31 30 29 28 27 26 25 24
BIT_NAME TRGCL63 TRGCL62 TRGCL61 TRGCL60 TRGCL59 TRGCL58 TRGCL57 TRGCL56
ACCESS_TYPE R0,W R0,W R0,W R0,W R0,W R0,W R0,W R0,W
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 23 22 21 20 19 18 17 16
BIT_NAME TRGCL55 TRGCL54 TRGCL53 TRGCL52 TRGCL51 TRGCL50 TRGCL49 TRGCL48
ACCESS_TYPE R0,W R0,W R0,W R0,W R0,W R0,W R0,W R0,W
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 15 14 13 12 11 10 9 8
BIT_NAME TRGCL47 TRGCL46 TRGCL45 TRGCL44 TRGCL43 TRGCL42 TRGCL41 TRGCL40
ACCESS_TYPE R0,W R0,W R0,W R0,W R0,W R0,W R0,W R0,W
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 7 6 5 4 3 2 1 0
BIT_NAME TRGCL39 TRGCL38 TRGCL37 TRGCL36 TRGCL35 TRGCL34 TRGCL33 TRGCL32
ACCESS_TYPE R0,W R0,W R0,W R0,W R0,W R0,W R0,W R0,W
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
[bit31:0] TRGCL63 to 32 : Trigger Status Clear bits
Bit Description
0 No effect.
1 A/D channel trigger status is cleared.
When this bit is set to "1", the corresponding bit in the ADC12Bn_TRGST1 register and TRGST bit in
the corresponding ADC12Bn_CHSTAT32 to 63 register are cleared.
If the corresponding trigger status is cleared during A/D conversion, the operation is dependent on the
setting of forced stop mode (ADC12Bn_CTRL.FSMD).
−
Forced stop is enabled (ADC12Bn_CTRL.FSMD = "1"): A/D conversion is stopped after interrupt
operation.
−
Forced stop is disabled (ADC12Bn_CTRL.FSMD = "0"): A/D conversion is not stopped (but A/D
conversion result is not updated). Hence, when the next conversion is already requested, the wait
time from trigger status flag clear to the start of next conversion can be up to the maximum A/D
conversion period.
This bit is identical to the TRGCL bit in the corresponding ADC12Bn_CHCTRL32 to 63 register.