Cypress S6J3200 Series, Manual

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CHAPTER 28:LCD Controller
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 1037
4. Operation
The following sections explain the operation of the LCD controller.
4.1.
Operation of LCD Controller/Driver (LCDC)
4.2.
1/2 Duty Output Waveform
4.3. 1/3 Duty Output Waveform
4.4.
1/4 Duty Output Waveform
4.5. Static Drive Output Waveform
4.1.
Operation of LCD Controller/Driver (LCDC)
The operation of LCD controller/driver (LCDC) is shown below.
1. Data Memory for Display
<Duty drive>
Set a value to the data memory for display (VRAM) in advance.
<Static drive>
Set a value to the data memory for display (LDR0, LDR1) in advance.
2. Write Necessary Settings to Each Register.
3. Output Pin
<Duty drive>
When a clock for frame cycle generation oscillates, waveforms that drive the LCD are output to the
common/segment output pins (COM0 to COM3, SEG0 to SEG31).
The content of the VRAM is read automatically in synchronization with the timing of the common signal
and output from the segment output pin.
(When the bit
of VRAM is set to "1", a selection waveform is output from the segment output pin.
When the bit
of VRAM is set to "0", a non-selection waveform is output from the segment output pin.)
Non-selection level waveforms are output from the COM2 and COM3 pins in 1/2 duty display mode and
from the COM3 pin in 1/3 duty display mode.
<Static drive>
When a clock for frame cycle generation oscillates, waveforms that drive the LCD are output to the
common/segment output pins (ST0 to ST8).
4. Output Waveform
<Duty drive>
Output waveforms drive in 2 frames alternating waveform according to the duty setting.
<Static drive>
Output waveforms drive in 1 frame alternating waveform.