Cypress S6J3200 Series, Manual

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CHAPTER 29:Indicator PWM
1096 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
3.5.
Indicator PWM Interrupts
This section provides information about indicator PWM interrupt request flags, interrupt enable bits, and
interrupt factors.
Notes:
−
The explanations in this section assume that PWM output is normal polarity. When inverse
polarity is set, invert the PWM output polarity shown in this explanation.
−
For details on how to set inverse polarity, see the OSEL bit in 4.1 Timer Control Register
(ITMCR).
3.5.1.
Interrupt Control Bits and Interrupt Factors
Table 3-1 lists interrupt control bits and interrupt factors. Underflow detection and detection of duty match
share the same interrupt factory output signals (IRQ_IND).
Table 3-1: Interrupt Control Bits and Interrupt Factors
Status Control Register (ISTC)
Interrupt Request
Flag Bit
Interrupt Request
Enable Bit
Interrupt Factor
Interrupt
Factor Output
Signal
Indicator PWM
UDIR : bit0 UDIE : bit4 Detection of underflow
IRQ_IND
DTIR : bit1 DTIE : bit5 Detection of duty match
An underflow in the PWM counter value causes the underflow interrupt request bit (ISTC:UDIR) of the
status control register (ISTC) to be set to "1". Enabling underflow interrupt request enable (ISTC:UDIE=1)
while this status exists will cause interrupt request output signal IRQ_IND to become "H". In the same way,
"1" is set to the duty match interrupt request bit (ISTC:DTIR) of the status control register (ISTC) when the
PWM counter count value matches the duty setting register (IPDUT) value. Enabling duty interrupt
request enable (ISTC:DTIE=1) while this status exists will cause interrupt request output signal IRQ_IND
to become "H".