Cypress S6J3200 Series, Manual

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CHAPTER 21:Ethernet MAC
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 669
4.19.
AXI Maximum Pipeline Register (ETHERNETn_axi_max_pipeline)
Description of AXI Maximum Pipeline register is shown. Used to set the maximum amount of outstanding
transactions on the AXI bus between AR/R channels and AW/W channels.
REGISTER_NAME ETHERNETn_axi_max_pipeline
OFFSET 0x054
ACCESS_SIZE W
MULTIPLE
NUMERIC_TYPE
OTHER
BIT_OFFSET 31 30 29 28 27 26 25 24
BIT_NAME Reserved
ACCESS_TYPE R0,WX
PROT_TYPE Wp
INITIAL_VALUE 0x00
BIT_OFFSET 23 22 21 20 19 18 17 16
BIT_NAME Reserved
ACCESS_TYPE R0,WX
PROT_TYPE Wp
INITIAL_VALUE 0x00
BIT_OFFSET 15 14 13 12 11 10 9 8
BIT_NAME aw2w_max_pipeline[7:0]
ACCESS_TYPE R/W
PROT_TYPE Wp
INITIAL_VALUE 0x01
BIT_OFFSET 7 6 5 4 3 2 1 0
BIT_NAME ar2r_max_pipeline[7:0]
ACCESS_TYPE R/W
PROT_TYPE Wp
INITIAL_VALUE 0x01
[bit31:16] Reserved
Always read "0". Writing has no effect.
[bit15:8] aw2w_max_pipeline:
Defines the maximum number of outstanding AXI write requests that can be issued by the DMA via the
AW channel.
Bits Description
0x00 The maximum number of outstanding write requests is 1.