Cypress S6J3200 Series, Manual

Page: 675 / 1355

CHAPTER 21:Ethernet MAC
674 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
4.23.
Specific Address Top i Register (ETHERNETn_spec_add_top_i)
(i=1 to 4)
The address stored in the Specific Address i registers are deactivated at reset or when their
corresponding Specific Address Bottom i register is written. They are activated when Specific Address
Top i register is written.
REGISTER_NAME ETHERNETn_spec_add_top_i
OFFSET (0x08C + ((i-1)*0x8))
ACCESS_SIZE W
MULTIPLE 1:4
NUMERIC_TYPE
OTHER
BIT_OFFSET 31 30 29 28 27 26 25 24
BIT_NAME Reserved filter_byte_mask[5:0]
ACCESS_TYPE R0,WX R/W
PROT_TYPE Wp
INITIAL_VALUE 0x0 0x00
BIT_OFFSET 23 22 21 20 19 18 17 16
BIT_NAME Reserved filter_type
ACCESS_TYPE R0,WX R/W
PROT_TYPE Wp
INITIAL_VALUE 0x00 0
BIT_OFFSET 15 14 13 12 11 10 9 8
BIT_NAME address[47:40]
ACCESS_TYPE R/W
PROT_TYPE Wp
INITIAL_VALUE 0x00
BIT_OFFSET 7 6 5 4 3 2 1 0
BIT_NAME address[39:32]
ACCESS_TYPE R/W
PROT_TYPE Wp
INITIAL_VALUE 0x00
[bit31:30] Reserved
Always read "0". Writing has no effect.
[bit29:24] filter_byte_mask: Filter byte mask
When high, the associated byte of the specific address will not be compared. Bit 24 controls whether
the first byte received should be compared. Bit 29 controls whether the last byte received should be
compared.