Cypress S6J3200 Series, Manual

Page: 1014 / 1355

CHAPTER 27:HyperBus Interface
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 1013
3.4.
FIFO
This section describes the FIFO for processing transaction request.
3.4.1.
ADR FIFO
ADR FIFO is composed of 46 bits width x 16 depth. This FIFO stores the control data of AXI bus
transaction which includes address, length, burst type and r/w flag.
3.4.2.
W DAT FIFO
The W DAT FIFO is composed of 40 bits width x 128 depth. This FIFO is used to store the write data,
valid information, and strobe information written from the AXI bus, and in order to receive the burst write
transaction without a wait on AXI bus.
3.4.3.
R DAT FIFO and RX FIFO
The RX FIFO is composed of 20 bits width x 256 depth. This FIFO is used to store the data which reads
from HyperBus, and stored data is outputted according to timing of CK on HyperBus to R DAT FIFO.
The R DAT FIFO is composed of 40 bits width x 128 depth. This FIFO is used to store the data read from
RX FIFO and the error detection information, and data stored is outputted according to timing of ACLK on
AXI bus. This error information is transferred to the master device by RRESP signals on AXI bus.
The FIFO for receiving data is divided into RX FIFO and R DAT FIFO in order to absorb the timing
difference between AXI and HyperBus.