Cypress S6J3200 Series, Manual

Page: 623 / 1355

CHAPTER 21:Ethernet MAC
622 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
[bit9] tx_start_clk: Transmit start
Bit Description
0 No effect
1 Starts transmission. Cleared by hardware.
[bit8] back_pressure: Back pressure
Bit Description
0 No effect
1 Will force collisions on all received frames in 10M of 100M half duplex mode.
[bit7] stats_write_en: Write enable for statistics register
Bit Description
0 Normal operation.
1 Statistics register can be written for functional test purposes.
[bit6] inc_all_stats_regs: Increment statistics register
Bit Description
0 No effect
1 Increment all statistics registers by 1 for functional test purposes. Cleared by hardware.
[bit5] clear_all_stats_regs: Clear statistics register
Bit Description
0 No effect
1 Clears all statistics registers. Cleared by hardware.
[bit4] man_port_en: Management port enable
Bit Description
0 Disable management ports. MDIO is forced to High-Z and MDC to "0".
1 Enable management ports.
[bit3] enable_transmit: Transmit enable
Bit Description
0
Transmission will stop immediately, the transmit pipeline and control registers will be cleared and the
transmit queue pointer registers (TX Buffer Queue Base Address, TX Buffer Queue 1 Base Address, TX
Buffer Queue 2 Base Address, and TX Buffer Queue 3 Base Address) will be reset to point to the start of
the transmit descriptor list.
1 Enable the Ethernet MAC to send data.
[bit2] enable_receive: Receive enable
Bit Description
0
Frame reception will stop immediately and the receive pipeline will be cleared. The receive queue pointer
register (ETHERNETn_receive_q_ptr) is unaffected.
1 Enable the Ethernet MAC to receive data.
[bit1:0] Reserved
Always read write value. Always write "0".