Cypress S6J3200 Series, Manual

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CHAPTER 21:Ethernet MAC
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 757
4.100.
PTP Peer Event Frame Received Nanoseconds Register
(ETHERNETn_tsu_peer_rx_nsec)
Description of PTP Peer Event Frame Received Nanoseconds register is shown.
REGISTER_NAME ETHERNETn_tsu_peer_rx_nsec
OFFSET 0x1FC
ACCESS_SIZE W
MULTIPLE
NUMERIC_TYPE
OTHER
BIT_OFFSET 31 30 29 28 27 26 25 24
BIT_NAME Reserved timer[29:24]
ACCESS_TYPE R0,WX R,WX
PROT_TYPE Wp
INITIAL_VALUE 0x0 0x00
BIT_OFFSET 23 22 21 20 19 18 17 16
BIT_NAME timer[23:16]
ACCESS_TYPE R,WX
PROT_TYPE Wp
INITIAL_VALUE 0x00
BIT_OFFSET 15 14 13 12 11 10 9 8
BIT_NAME timer[15:8]
ACCESS_TYPE R,WX
PROT_TYPE Wp
INITIAL_VALUE 0x00
BIT_OFFSET 7 6 5 4 3 2 1 0
BIT_NAME timer[7:0]
ACCESS_TYPE R,WX
PROT_TYPE Wp
INITIAL_VALUE 0x00
[bit31:30] Reserved
Always read "0". Writing has no effect.
[bit29:0] timer: PTP Peer Event Frame Received Nanoseconds
The register is updated with the value that the IEEE 1588 Timer Nanoseconds register held when the
SFD of a PTP receive peer event crosses the MII interface. The actual update occurs when the
Ethernet MAC recognizes the frame as a PTP Pdelay_Req or Pdelay_Resp frame. An interrupt is
issued when the register is updated.