Cypress S6J3200 Series, Manual

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CHAPTER 21:Ethernet MAC
748 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
4.92.
IEEE 1588 Timer Increment Register (ETHERNETn_tsu_timer_incr)
Description of IEEE 1588 Timer Increment register is shown.
REGISTER_NAME ETHERNETn_tsu_timer_incr
OFFSET 0x1DC
ACCESS_SIZE W
MULTIPLE
NUMERIC_TYPE
OTHER
BIT_OFFSET 31 30 29 28 27 26 25 24
BIT_NAME Reserved
ACCESS_TYPE R0,WX
PROT_TYPE Wp
INITIAL_VALUE 0x00
BIT_OFFSET 23 22 21 20 19 18 17 16
BIT_NAME num_incs[7:0]
ACCESS_TYPE R/W
PROT_TYPE Wp
INITIAL_VALUE 0x00
BIT_OFFSET 15 14 13 12 11 10 9 8
BIT_NAME alt_count[7:0]
ACCESS_TYPE R/W
PROT_TYPE Wp
INITIAL_VALUE 0x00
BIT_OFFSET 7 6 5 4 3 2 1 0
BIT_NAME count[7:0]
ACCESS_TYPE R/W
PROT_TYPE Wp
INITIAL_VALUE 0x00
[bit31:24] Reserved
Always read "0". Writing has no effect.
[bit23:16] num_incs: Number of incs before alt inc
The number of increments after which the alternative increment is used.
[bit15:8] alt_count: Alternative count of nanoseconds
Alternative count of nanoseconds by which the IEEE 1588 Timer Nanoseconds register will be
incremented each clock cycle.