Cypress S6J3200 Series, Manual

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CHAPTER 21:Ethernet MAC
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 743
4.87.
IEEE 1588 Timer Increment Sub Nanoseconds Register
(ETHERNETn_tsu_timer_incr_sub_nsec)
Description of IEEE 1588 Timer Increment Sub Nanoseconds register is shown.
REGISTER_NAME ETHERNETn_tsu_timer_incr_sub_nsec
OFFSET 0x1BC
ACCESS_SIZE W
MULTIPLE
NUMERIC_TYPE
OTHER
BIT_OFFSET 31 30 29 28 27 26 25 24
BIT_NAME Reserved
ACCESS_TYPE R0,WX
PROT_TYPE Wp
INITIAL_VALUE 0x00
BIT_OFFSET 23 22 21 20 19 18 17 16
BIT_NAME Reserved
ACCESS_TYPE R0,WX
PROT_TYPE Wp
INITIAL_VALUE 0x00
BIT_OFFSET 15 14 13 12 11 10 9 8
BIT_NAME count[15:8]
ACCESS_TYPE R,WX
PROT_TYPE Wp
INITIAL_VALUE 0x00
BIT_OFFSET 7 6 5 4 3 2 1 0
BIT_NAME count[7:0]
ACCESS_TYPE R,WX
PROT_TYPE Wp
INITIAL_VALUE 0x00
[bit31:16] Reserved
Always read "0". Writing has no effect.
[bit15:0] count: IEEE 1588 Timer Increment [15:0]
Lower significant bits of IEEE 1588 Timer Increment [15:0] register giving a 24-bit timer_increment
counter. These bits are the sub-ns value which the IEEE 1588 Timer will increment each clock cycle. Bit
n = 2(n-16) nsec giving a resolution of approximately 15.2E-15 sec.