Cypress S6J3200 Series, Manual

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CHAPTER 3:Product Description
48 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
Function Register Bit Offset Access Error Type
MEDIA LOCAL BUS INTERFACE
(Media LB)
MLBn_DCCR bit [15:8] Reserved Write(B) Bus error
MLBn_SSCR bit [31:8] Reserved Write(B,H) Bus error
MLBn_SDCR Whole register Write(B,H,W) Bus error
MLBn_SMCR bit [31:8] Reserved Write(B,H) Bus error
MLBn_VCCR Whole register Write(B,H,W) Bus error
MLBn_CICR Whole register Write(B,H,W) Bus error
MLBn_CSCR0-15 bit [31:24] Write(B) Bus error
MLBn_CCBCR0-15 Whole register Write(B,H,W) Bus error
MLBn_MID Whole register Write(B,H,W) Bus error
3.2.1.
Error Response for optional function
Error response is generated when access occurs to the following optional function if product doesn’t
support them. For optional function of product, see the “Optional Function”.
Start Address End Address Function Remark
5028_1000 5028_1FFF Hyper Bus ch.2 Control
B800_0000 B800_07FF EHTERNET
B800_0800 B800_0BFF MPU_AXI This function is supported with ETHERNET
B800_8000 B800_83FF MLB
B800_8400 B800_87FF MPU_AHB This function is supported with MLB
3.3.
Register Initial Value
The table shows initial value of Register bit which is uniquely specified for the product series.
Register Bit Attribute Initial Value Description
SYSC0_RUNREGCFGR RVSEL R0/W0 0 0 should be written. Prohibit setting 1.
SYSC0_STSREGCFGR RVSEL R,WX 0
-
SYSC0_APPREGCFGR RVSEL R,WX 0
-
SYSC0_APPLVDCFGR LVDL1S R,WX 0
-
SYSC0_APPLVDCFGR LVDL1V R,WX 10
-
SYSC0_APPLVDCFGR LVDL1E R,WX 1
-
SYSC0_APPLVDCFGR LVDL2S R,WX 0
-
SYSC0_APPLVDCFGR LVDL2V R,WX 00
-
SYSC0_APPLVDCFGR LVDL2E R,WX 0 or 1 * See the note below.
SYSC0_APPLVDCFGR LVDH1S R,WX 0
-
SYSC0_APPLVDCFGR LVDH1V R,WX 0110
-
SYSC0_APPLVDCFGR LVDH1E R,WX 1
-
SYSC0_APPLVDCFGR LVDH2S R,WX 0
-
SYSC0_APPLVDCFGR LVDH2V R,WX 0000
-
SYSC0_APPLVDCFGR LVDH2E R,WX 0
-
SYSC0_STSLVDCFGR LVDL1R R,WX 1
-