Cypress S6J3200 Series, Manual

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CHAPTER 21:Ethernet MAC
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 781
[bit11] resp_not_ok: BRESP not OK
Bit Description
0 Interrupt de-asserted.
1 Interrupt asserted. Set when the DMA block sees BRESP not OK.
[bit10] receive_overrun: Receive over run
Bit Description
0 Interrupt de-asserted.
1 Interrupt asserted. Set when the receive over run status bit (ETHERNETn_receive_status[2]) gets set.
[bit9:8] Reserved
Always read "0". Writing has no effect.
[bit7] transmit_complete: Transmit complete
Bit Description
0 Interrupt de-asserted.
1 Interrupt asserted. Set when when a frame has been transmitted.
[bit6] amba_error: Transmit frame corruption due to AMBA AXI error
Bit Description
0 Interrupt de-asserted.
1
Interrupt asserted. Set if an error occurs whilst midway through reading transmit frame from system
memory, including BRESP errors and buffers exhausted mid frame.
[bit5] retry_limit_exceeded_or_late_collision: Retry limit exceeded
Bit Description
0 Interrupt de-asserted.
1 Interrupt asserted. Transmit error.
[bit4:3] Reserved
Always read "0". Writing has no effect.
[bit2] rx_used_bit_read: RX used bit read
Bit Description
0 Interrupt de-asserted.
1 Interrupt asserted. Set when a receive buffer descriptor is read with its used bit set.
[bit1] receive_complete: Receive complete
Bit Description
0 Interrupt de-asserted.
1 Interrupt asserted. Set when a frame has been stored in memory.
[bit0] Reserved
Always read "0". Writing has no effect.