Cypress S6J3200 Series, Manual

Page: 430 / 1355

CHAPTER 18:Sound Generator
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 429
3.7.2.
In Case of DMA Transfer with 2-byte Size x 2 Is Made N Times
Figure 3
-
10 Sound Generator Operation with DMA (When DMA Transfer with 2-byte Size x 2 Is Made N Times)
External Sound
Output
SG RAM DMAC MCU
Address of transfer source/destination, block transfer,
Transfer size, block size, number of transfer, etc.
Sound Control Register (SGCR)
Start
SGO, SGA output #n
SGO, SGA output
#n+1
∬ ∬ ∬ ∬ ∬
SGO, SGA output
#n+m
(1)
(5)
Interrupt clear
Interrupt
This interrupt is asserted because the sound
generator outputs tone pulses to the number set in
the Time Cycle Register (SGTCR) and Tone
Output Number Register (SGNR).
:
:
SGO, SGA output
#n+m+1
Interrupt clear
Interrupt
(9)
Interrupt
Interrupt
Interrupt clear
Sound Control Register (SGCR)
Stop
SGO, SGA output
#n+m+x+1
:
:
If the current tone cycle is outputting, the SGO
and SGA output stops when the current tone cycle
output is finished.
(12)
(14)
This interrupt is asserted because the Sound
Generator outputs tone pulses to the number set
in the Time Cycle Register (SGTCR) and Tone
Output Number Register (SGNR).
∬ ∬ ∬ ∬ ∬
SGO, SGA output
#n+m+x
:
:
(15)
If this period is over
“(Frequency Data [SGFR] +1) x 1 PWM cycle”
and the stop instruction is set as SGCR:ST=
”0”,
the SGO and SGA are output.
(16)
(17)
DMA Transfer Intermediate Register (SGDMAR)
[Frequency Data,Tone Output Number Register]
DMA Transfer Intermediate Register (SGDMAR)
[Increase and Decrease Data Register]
2 bytes x2
DMA transfer #2
Within
(Frequency Data [SGFR] +1)
x 1 PWM cycle
DMA Transfer Intermediate Register (SGDMAR)
[Frequency Data,Tone Output Number Register]
DMA Transfer Intermediate Register (SGDMAR)
[Increase and Decrease Data Register]
2 bytes x2
DMA transfer #N-1
Within
(Frequency Data [SGFR] +1)
x 1 PWM cycle
DMA Transfer Intermediate Register (SGDMAR)
[Frequency Data,Tone Output Number Register]
DMA Transfer Intermediate Register (SGDMAR)
[Increase and Decrease Data Register]
2 bytes x2
DMA transfer #N
Within
(Frequency Data [SGFR] +1)
x 1 PWM cycle
(10)
(11)
*3
*3
*4
(13)
DMA Transfer Update Enable Register (SGDER)
Enabling data update for {frequency,
tone output number, and increase/decrease}
(2)
Amplitude Data Register (SGDER)
Time Cycle Register (SGTCR),
PWM Cycle Data Register (SGPCR)
(3) *1
SGO, SGA output #1
Interrupt clear
∬ ∬ ∬ ∬ ∬
Interrupt
DMA Transfer Intermediate Register (SGDMAR)
[Frequency Data,Tone Output Number Register]
DMA Transfer Intermediate Register (SGDMAR)
[Increase and Decrease Data Register]
2 bytes x2
DMA transfer #1
Within
(Frequency Data [SGFR] +1)
x 1 PWM cycle
(6)
(7)
:
:
An interrupt is asserted when the generator is
enabled to start (SGCR:ST=
”1”) because the DMA
transfer start interrupt setting enable bit is set to
“enabled” (SGCR:DMA=”1”).
This is the first DMA transfer request.
(8)
The sound output starts because access with 2-
byte size x2 is given on the DMA Transfer
Intermediate Register (SGDMAR).
*2
Sound Control Register (SGCR)
- Setting and enabling of increase/decrease
- Enabling prescaler, tone and interrupt
Interrupt Clear Register (SGCCR)
- Initializing interrupt
(4)