CHAPTER 18:Sound Generator
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
433
(1) Software makes initial settings to those registers which are needed in DMA transfer. The DMA transfer
is based on a block data of "1-byte size x 2", and this block can be repeated N times. DMAC sets
following registers to prepare for a DMA transfer, through the "DMA Transfer Intermediate Register
(SGDMAR)".
-
Frequency Data Register (SGFR)
The destination address of the DMA transfer is a fixed one on the "DMA Transfer Intermediate Register
(SGDMAR)".
(2) Software configures the "DMA Transfer Update Enable Register (SGDER)" to enable the automatic
update of the following registers during DMA transfer.
-
Frequency Data Register (SGFR)
(3) Software configures the "DMA Transfer Update Enable Register (SGDER)" to disable the automatic
update of the following registers during DMA transfer.
-
Amplitude Data Register (SGAR)
-
Tone Output Number Register (SGNR)
-
Time Cycle Register (SGTCR)
-
Increase and Decrease Data Register (SGIDR)
-
PWM Cycle Data Register (SGPCR)
(*1: Set values to these registers which are not automatically updated.)
(4) Software initialize Interrupt status bit (SGCR.INT) by writing "1" to Interrupt status clear bit
(SGCCR.INTC). Then, the software configures the Sound Control Register (SGCR) in the needed mode,
and this must include the following bit operations.
-
DMA transfer start interrupt setting enable bit (SGCR.DMA) to "1"(enabled)
-
Interrupt enable bit (SGCR.INTE) to "1"(enabled)
(5) Write "1" to the Start bit (SGCR.ST).
(6) The interrupt occurs immediately after setting Start bit (SGCR.ST), since the Sound Generator is
enabled on DMA transfer (SGCR.DMA="1"). An Interrupt request (PIRQ) is asserted, and this interrupt is
used as a DMA transfer request.
(7) DMAC clears the interrupt, and write registers in the Sound Generator through the "DMA Transfer
Intermediate Register (SGDMAR)". This operation configures the following register.
-
Frequency Data Register (SGFR)
(*2: DMA block size must to be "1-byte size x 1" for the access to "DMA Transfer Intermediate Register
(SGDMAR)")
(8) The outputs of SGO and SGA start, according to the register settings above.
(9) The Tone pulse counter counts the number of tone pulses. When the following conditions are satisfied,
the interrupt is generated.
-
Tone pulse counter is 0x00
-
Decrement counter is 0x00
-
At the rising edge of SGO
(10) DMAC clears the interrupt, and write registers in the Sound Generator through the "DMA Transfer
Intermediate Register (SGDMAR)".
(*3: DMA block size must to be "1-byte size x 1" for the access to "DMA Transfer Intermediate Register
(SGDMAR)")
(11) The Sound Generator keeps outputting SGO and SGA, according to the register settings above.
Summary of Contents for S6J3200 Series
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