Cypress S6J3200 Series, Manual

Page: 19 / 1355

Table of Contents
18 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
9. Notes ................................................................................................................................ 1089
CHAPTER 29: Indicator PWM ......................................................................................................... 1090
1. Overview .......................................................................................................................... 1091
2. Configuration and Block Diagram ..................................................................................... 1091
3. Operation of Indicator PWM ............................................................................................. 1092
3.1. Indicator PWM Timer .......................................................................................... 1092
3.2. PWM Timer Count Operation Start ..................................................................... 1093
3.3. Timer Count Operation Stop ............................................................................... 1094
3.4. Counter Value Updating while PWM Counter Operation is in Progress .............. 1095
3.5. Indicator PWM Interrupts .................................................................................... 1096
3.6. Operation Flowchart ........................................................................................... 1098
4. Registers .......................................................................................................................... 1100
4.1. Timer Control Register (ITMCR) ......................................................................... 1101
4.2. Count Control Register (ICNTCR) ...................................................................... 1104
4.3. Status Control Register (ISTC) ........................................................................... 1106
4.4. Status Control Clear Register (ISTCC) ............................................................... 1108
4.5. Status Control Set Register (ISTCS) ................................................................... 1110
4.6. PWM Cycle Setting Register (IPCSR) ................................................................. 1112
4.7. PWM Duty Setting Register (IPDUT) ................................................................... 1113
5. Precautions for Using This Device .................................................................................... 1115
5.1. Notes to Observe When Accessing a Register .................................................... 1115
5.2. Indicator PWM Operation Precautions ................................................................ 1115
CHAPTER 30: FPD-Link Converter ................................................................................................. 1116
1. Overview .......................................................................................................................... 1117
2. Configuration and Block Diagram ..................................................................................... 1117
3. Operation .......................................................................................................................... 1119
3.1. Register IF ........................................................................................................... 1119
3.2. Output Signal Selection for FPD-Link .................................................................. 1119
3.3. FPD-Link Control ................................................................................................ 1120
3.4. Power ON/Power DOWN Sequence .................................................................. 1120
4. Registers .......................................................................................................................... 1122
4.1. Unlock Registers (UNLOCK) .............................................................................. 1123
4.2. Control0 Registers (CTRL0) ............................................................................... 1125
4.3. Control1 Registers (CTRL1) ............................................................................... 1127
4.4. Channel Select Registers (CH_SEL) .................................................................. 1130
4.5. TXn Configuration Registers (TXn_CONF (n: 0 to 4)) ........................................ 1131
4.6. GDC Control Register (GDCCR) ........................................................................ 1133
CHAPTER 31: Memory Protection Unit for AXI ................................................................................ 1135
1. Overview .......................................................................................................................... 1136
2. Configuration and Block Diagram ..................................................................................... 1137
3. Operation of the MPU AXI ................................................................................................ 1138
4. Registers .......................................................................................................................... 1144
4.1. MPU AXI Control Register (MPUXn_CTRL0) ..................................................... 1147
4.2. MPU AXI NMI Enable Register (MPUXn_NMIEN) .............................................. 1149
4.3. MPU AXI Write Error Control Register (MPUXn_WERRC) ................................. 1150
4.4. MPU AXI Write Error Address Register (MPUXn_WERRA)................................ 1151
4.5. MPU AXI Read Error Control Register (MPUXn_RERRC) ................................. 1152
4.6. MPU AXI Read Error Address Register (MPUXn_RERRA) ................................ 1153