Cypress S6J3200 Series, Manual

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CHAPTER 21:Ethernet MAC
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 813
4.134.
Interrupt Mask Queue i Register (ETHERNETn_int_mask_qi) (i=1 to
3)
The Interrupt Mask Queue i register is a read only register indicating which interrupts are masked. All bits
are set at reset and can be reset individually by writing to the Interrupt Enable Queue i register or set
individually by writing to the Interrupt Disable Queue i register. Having separate address locations for
enable and disable saves the need for performing a read modify write when updating the Interrupt Mask
Queue i register. For test purposes there is a write-only function to this register that allows the bits in the
Interrupt Status Queue i register to be set or cleared, regardless of the state of the mask register
REGISTER_NAME ETHERNETn_int_mask_qi
OFFSET (0x640 + ((i-1)*0x4))
ACCESS_SIZE W
MULTIPLE 1:3
NUMERIC_TYPE
OTHER
BIT_OFFSET 31 30 29 28 27 26 25 24
BIT_NAME Reserved
ACCESS_TYPE R0,WX
PROT_TYPE Wp
INITIAL_VALUE 0x00
BIT_OFFSET 23 22 21 20 19 18 17 16
BIT_NAME Reserved
ACCESS_TYPE R0,WX
PROT_TYPE Wp
INITIAL_VALUE 0x00
BIT_OFFSET 15 14 13 12 11 10 9 8
BIT_NAME Reserved
resp_not_o
k_interrupt_
mask
receive_ove
rrun_interru
pt_mask
Reserved
ACCESS_TYPE R0,WX R,W R,W R0,WX
PROT_TYPE Wp
INITIAL_VALUE 0x0 1 1 0x0
BIT_OFFSET 7 6 5 4 3 2 1 0
BIT_NAME
transmit_co
mplete_inte
rrupt_mask
transmit_fra
me_corrupti
on_due_to_
amba_error
_interrupt_
mask
retry_limit_e
xceeded_or
_late_collisi
on_interrupt
_mask
Reserved
rx_used_bit
_read_interr
upt_mask
receive_co
mplete_inte
rrupt_mask
Reserved
ACCESS_TYPE R,W R,W R,W R0,WX R,W R,W R0,WX
PROT_TYPE Wp
INITIAL_VALUE 1 1 1 0 1 1 0