Cypress S6J3200 Series, Manual

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CHAPTER 21:Ethernet MAC
590 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
TX Packet
Buffer
RX Packet
Buffer
TX DMA
RX DMA
Status &
Statistics
Registers
APB
Slave
Interface
MAC
Transmitter
MAC
Receiver
TX Packet
Buffer
Memory
RX Packet
Buffer
Memory
AXI
Master
Interface
AXI Bus
TX MII
RX MII
APB Bus
Frame
Filtering
MDIO
Control
Register
Ethernet MAC
Figure 3-1: Ethernet MAC Data Path Structure
In the transmit direction, the Ethernet MAC DMA will continue to fetch packet data up to a limit of 256
packets, or until the TX Packet Buffer Memory is full. The size of the TX Packet Buffer Memory is 16
Kbytes (4 Kbytes per queue). In the receive direction, if the RX Packet Buffer Memory becomes full, then
an overflow will occur. An overflow will also occur if the limit of 256 packets is breached. The size of the
RX Packet Buffer Memory is 4 Kbytes.
 Transmit Packet Buffer
The Transmit Packet Buffer (TX Packet Buffer) will continue attempting to fetch frame data from the
system memory until the TX Packet Buffer Memory is full, at which point it will attempt to maintain its full
level.
To accommodate the status and statistics associated with each frame, 2 words per packet are reserved
at the end of the packet data. If the packet was bad and requires to be dropped, the status and
statistics are the only information held on that packet. Storing the status in the packet buffer is required
in order to decouple the TX DMA interface of the buffer from the MAC Transmitter interface, to update
the MAC status/statistics and to generate interrupts in the order in which the packets that they
represent were fetched from the system memory.