Cypress S6J3200 Series, Manual

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CHAPTER 21:Ethernet MAC
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 643
BIT_NAME
transmit_co
mplete
amba_error
retry_limit_e
xceeded
Reserved
tx_used_bit
_read
rx_used_bit
_read
receive_co
mplete
manageme
nt_frame_s
ent
ACCESS_TYPE R,W1C R,W1C R,W1C R,WX R,W1C R,W1C R,W1C R,W1C
PROT_TYPE Wp
INITIAL_VALUE 0 0 0 0 0 0 0 0
[bit31:30] Reserved
Always read "0". Writing has no effect.
[bit29] tsu_timer_comparison_interrupt: IEEE 1588 Timer comparison interrupt
Bit Description
0 Interrupt de-asserted.
1 Interrupt asserted. Indicates when IEEE 1588 Timer count value is equal to programmed value.
[bit28] Reserved
Writing has no effect. This bit will read “1” if bit 28 of Interrupt Mask register is set otherwise it will read
“0”.
[bit27] receive_lpi_indication_status_bit_change: Receive LPI Indication Status Bit
change
Bit Description
0 Interrupt de-asserted.
1 Interrupt asserted. Indicates that Receive LPI Indication Status bit has changed.
[bit26] tsu_seconds_register_increment: IEEE 1588 Timer Seconds register increment
Bit Description
0 Interrupt de-asserted.
1 Interrupt asserted. Indicates that IEEE 1588 Timer Seconds register was incremented.
[bit25] ptp_pdelay_resp_frame_transmitted: PTP Pdelay_Resp frame transmitted
Bit Description
0 Interrupt de-asserted.
1 Interrupt asserted. Indicates a PTP Pdelay_Resp frame has been transmitted.
[bit24] ptp_pdelay_req_frame_transmitted: PTP Pdelay_Req frame transmitted
Bit Description
0 Interrupt de-asserted.
1 Interrupt asserted. Indicates a PTP Pdelay_Req frame has been transmitted.
[bit23] ptp_pdelay_resp_frame_received: PTP Pdelay_Resp frame received
Bit Description
0 Interrupt de-asserted.
1 Interrupt asserted. Indicates a PTP Pdelay_Resp frame has been received.