Cypress S6J3200 Series, Manual

Page: 337 / 1355

CHAPTER 15:12-/10-/8-bit Analog to Digital Converter
336 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
This bit is set if any conversion request, dedicated to the corresponding logical channel, occurs
(software, hardware, trigger by completion of preceding channel or idle trigger). Moreover, the bit is set
if:
−
The group of the corresponding logical channel is interrupted just before a channel configured as
"restart" channel (ADC12Bn_CHCTRL32 to 63.RSMRST = "10")
The channel is the start channel of the group or the last already converted channel configured as
"resume" channel (ADC12Bn_CHCTRL32 to 63.RSMRST = "01").
This bit is cleared under one of the following conditions:
−
Completion of the logical channel conversion (the last conversion in the case of multiple conversion
channels), at the same time the conversion done interrupt flag is set
−
The corresponding group processing is interrupted just before the conversion of this channel is
started and the channel is not configured as "resume" channel (ADC12Bn_CHCTRL0 to
31.RSMRST = "01"). Instead, the group interrupted interrupt flag is set
−
Writing "1" to the corresponding bit in the ADC12Bn_TRGCL0 register or writing "1" to the
corresponding ADC12Bn_CHCTRL0 to 31.TRGCL bit.
When setting and clearing of the bit takes place at the same time, clearing has priority.
This bit is identical to the TRGST bit in the corresponding ADC12Bn_CHSTAT0 to 31 register.