Cypress S6J3200 Series, Manual

Page: 1254 / 1355

CHAPTER 33:Graphics Subsystem
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 1253
 vram_errinj_ecc_s0_lo
REGISTER_NAME vram_errinj_ecc_s0_lo
OFFSET 0x10x118
ACCESS_SIZE W
MULTIPLE
NUMERIC_TYPE
OTHER
ECC error injection for S0 interface (check bits for lower 32bits).
BIT_OFFSET 31 30 29 28 27 26 25 24
BIT_NAME Reserved
ACCESS_TYPE R0,WX
PROT_TYPE RpL/WpL
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 23 22 21 20 19 18 17 16
BIT_NAME Reserved vram_errinj_ecc_s0_lo[19:16]
ACCESS_TYPE R0,WX R/W
PROT_TYPE RpL/WpL
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 15 14 13 12 11 10 9 8
BIT_NAME vram_errinj_ecc_s0_lo[15:8]
ACCESS_TYPE R/W
PROT_TYPE RpL/WpL
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 7 6 5 4 3 2 1 0
BIT_NAME vram_errinj_ecc_s0_lo[7:0]
ACCESS_TYPE R/W
PROT_TYPE RpL/WpL
INITIAL_VALUE 0 0 0 0 0 0 0 0
[bit19:0] vram_errinj_ecc_s0_lo : VRAM Error Injection for ECC check bits of S0
interface lower part
Each bit set in this register emulates a bit-flip in the corresponding ECC check bit for the read data
(lower 32 bit) of the S0 interface