CHAPTER 15:12-/10-/8-bit Analog to Digital Converter
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S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
positive counter and negative counter are stopped as long as the pulse counter interrupt flag of the
appropriate channel is set.
This bit is cleared by writing "1" to the corresponding bit in the ADC12Bn_PCIRQC0 register.
This bit is identical to the PCIRQ bit in the corresponding ADC12Bn_CHSTAT0 to 31 register.
Summary of Contents for S6J3200 Series
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