CHAPTER 33:Graphics Subsystem
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
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If floating part of the DIVIDER is >= 0.5: fDSP_CLK_max = fREF_CLK / (2 x int(dsp0/1_ClockDivider) +
1)
If floating part of the DIVIDER is < 0.5: fDSP_CLK_max = fREF_CLK / (2 x int(dsp0/1_ClockDivider) )
(With DIVIDER = fREF_CLK / fDSP_CLK)
In case of RSDS:
Also unless the clock divider implemented is an integer, the duty cycle of the display clock is not 50%.
The display clock consists of higher frequencies of fDSP_CLK_max = fREF / int(DIVIDER) and lower
frequencies of fDSP_CLK_max = fREF / int(1)
This needs to be considered for the RSDS case where both edges of the display clock are used.
Summary of Contents for S6J3200 Series
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