Cypress S6J3200 Series, Manual

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CHAPTER 31:Memory Protection Unit for AXI
1160 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
1. After the system reset, the software detects the module ID number of MPU AXI, by reading the
MPUXn_MID register. This helps it in identifying the attributes and capabilities supported by the MPU AXI
module. Then the software configures MPU AXI by setting appropriate registers.
2. By default, MPU AXI propagates the MPUXn_CTRL0:NMI flag to the CPU through the Interrupt
Controller. If polling mode is desired, the software can reset the MPUXn_NMIEN:NMIEN bit to "0".
Note:
−
The MPUXn_NMIEN:NMIEN can be written only once after reset. Subsequent write accesses to
this bit have no visible impact on the state of this bit.
3. When the NMI is triggered or is in polling mode, if the software detects during its polling cycle that the
MPUXn_CTRL0:NMI status flag is set, the CPU is invoked. This would read the status information
collected and stored by MPU AXI in its CSR.
4. The software diagnoses the information about the transaction for which memory protection violation
was detected and initiates a corrective action (if any).
5. Once the software has processed the information from the status registers, it shall clear the
MPUXn_CTRL0:NMI flag by writing a "1" to the MPUXn_CTRL0:NMICL bit. Clearing
MPUXn_CTRL0:NMI flag ensures that the MPU AXI starts monitoring the AXI master interfaces again for
checking memory protection violation.
Note:
−
Software may clear the NMI flag before taking corrective action, hence steps 4 and 5 can be
interchanged.