CHAPTER 26:PCMPWM
1004
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
[bit2] UDRN : FIFO Under-Run Error
When this bit is written as "1", the FIFO under-run error interrupt is cleared.
Bit
Description
0
Leave the FIFO under-run error interrupt unchanged
1
Writing a "1" to this bit clears the FIFO under-run error interrupt. This bit is always read as "0".
[bit1] OVFL : FIFO Overflow Error
When this bit is written as "1", the FIFO overflow error interrupt is cleared.
Bit
Description
0
Leave the FIFO overflow error interrupt unchanged
1
Writing a "1" to this bit clears the FIFO overflow error interrupt. This bit is always read as "0".
[bit0] DREQ : Data Request
When this bit is written as "1", the data request interrupt is cleared.
Bit
Description
0
Leave the data request interrupt unchanged
1
Writing a "1" to this bit clears the data request interrupt. This bit is always read as "0".
Summary of Contents for S6J3200 Series
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