Cypress S6J3200 Series, Manual

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Table of Contents
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 15
3. Operation ............................................................................................................................ 880
3.1. Initialization ........................................................................................................... 880
3.2. Using DMA Transfers to Update DADR Register .................................................. 881
3.3. Output Data Values of the Analog DAC ................................................................ 881
3.4. Switching Clock Frequencies of the Analog DAC ................................................. 882
3.5. Minimum Writing Interval between the DAOSR and DACR Registers .................. 882
3.6. Interrupt ................................................................................................................ 882
3.7. AHB Slave Interface ............................................................................................. 883
3.8. FIFO ..................................................................................................................... 883
3.9. Frequency of CLKPI and CLKDA ......................................................................... 884
3.10. Sampling Frequency and Oversampling Setting of D/A Converter ....................... 884
3.11. Output Stop Control of Analog DAC ..................................................................... 886
3.12. Bridge-tied Load (BTL) ......................................................................................... 886
4. Registers ............................................................................................................................ 887
4.1. DAC Over Sampling Register(DAOSR) ................................................................ 887
4.2. DAC Configuration (DACR) .................................................................................. 889
4.3. DAC BUSY Register(DABUSY) ............................................................................ 891
4.4. DAC Control Register(DACTRL) .......................................................................... 893
4.5. DAC FLUSH Register(DAFLUSH) ........................................................................ 895
4.6. Interrupt Enable Register(INTREN) ...................................................................... 897
4.7. Interrupt State Register (INTRSTAT) .................................................................... 899
4.8. Interrupt Clear Register (INTCTR) ........................................................................ 901
4.9. DAC Polarity Configuration Register (DPCR) ....................................................... 903
4.10. Data 0..15 Register (DADR) ................................................................................. 905
CHAPTER 24: Inter-IC Sound (I2S) ................................................................................................... 906
1. Overview ............................................................................................................................ 907
2. Configuration and Block Diagram ....................................................................................... 908
3. Operations of the I2S .......................................................................................................... 909
3.1. I2S Frame Construction ........................................................................................ 909
3.2. I2S Configuration and Operation Modes .............................................................. 911
3.3. Bit Alignment ........................................................................................................ 917
3.4. FIFO Construction ................................................................................................ 919
3.5. Caution Summary ................................................................................................. 922
4. Registers ............................................................................................................................ 923
4.1. Reception FIFO Data Register (I2Sn_RXFDAT0 to 15) ........................................ 926
4.2. Transmission FIFO Data Register (I2Sn_TXFDAT0 to 15) ................................... 928
4.3. Control Register (I2Sn_CNTREG) ........................................................................ 929
4.4. Channel Control Register 0 (I2Sn_MCR0REG) .................................................... 934
4.5. Channel Control Register 1 (I2Sn_MCR1REG) .................................................... 938
4.6. Channel Control Register 2 (I2Sn_MCR2REG) .................................................... 939
4.7. Operation Control Register (I2Sn_OPRREG) ....................................................... 940
4.8. Software Reset Register (I2Sn_SRST) ................................................................ 942
4.9. Interrupt Control Register (I2Sn_INTCNT) ........................................................... 943
4.10. Status Register (I2Sn_STATUS) ........................................................................... 947
4.11. DMA Activate Register (I2Sn_DMAACT) .............................................................. 951
4.12. Debug Register (I2Sn_DEBUG) ........................................................................... 953
4.13. Module ID Register (I2Sn_MIDREG) .................................................................... 955