Cypress S6J3200 Series, Manual

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CHAPTER 24:Inter-IC Sound (I2S)
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 907
1.
Overview
This section describes the features and the block diagram of the I2S module.
Also refer to the chapter of "Sound System Configuration" how to configure the I2S which is connected to
the Sound Mixer.
I2S module is a full duplex, synchronous serial audio interface for multichannel specification. It can be
configured to various frame formats by register setting.
This module can be set to operate as master and slave. In the master mode, clock (SCK) and frame
synchronous signal (WS) are output to the external slave. In the slave mode, they are input from the
external master.
During the master mode, SCK clock can be output by dividing external clock or internal clock (it is
selectable by register). Frame synchronous signal can be generated by free-running or burst mode
(generated only when there is transmission data).
This module has transmission/reception FIFOs, and their depths depend on the mode:
In transmission only mode, there is a 132-word 32-bit transmission FIFO. In reception only mode, there is
a 132-word 32-bit reception FIFO. This module can also be configured in simultaneous mode.
Simultaneous mode operates with a 66-word 32-bit transmission FIFO and a 66-word 32-bit reception
FIFO.
Internal transfer between transmission and reception FIFO and internal system memory can be
performed by DMA, interrupt, and polling.
Features of I2S
I2S interface has the following features:

Programmable master/slave operations

Support of transmission only, reception only and simultaneous transmission/reception modes

Selecting 1 sub frame and 2 sub frame constructions

Setting up to 32 channels to each sub frame

Individually setting number of channel in each sub frame

Individually setting channel length of each sub frame (number channel bit)

Individually setting word length in channel of each sub frame

Setting valid/invalid of each channel in each sub frame. Data is not sent or received to invalid channel

Setting word length from 7 to 32 bits

Programming frequency of frame synchronous signal

Setting up to 3072 bits in 1 frame

Programming width of frame synchronous signal (1 bit or 1 channel length)

Programming phase of frame synchronous signal (0-bit or 1-bit delay)

Setting polarity of frame synchronous signal

Setting polarity of serial bit clock

Programming sampling point of received data (center or at the end of received data)

Selecting clock frequency source of serial bit clock in the master mode (internal and external clock)

Setting clock frequency dividing ratio in the master mode

Frequency of SCK = (frequency of internal clock or external clock) / (2 x I2Sn_CNTREG:CKRT[5:0])

Frequency dividing ratio is settable within 0-126 in multiple of 2 (when the ratio is "0", frequency dividing
source is bypassed)

Data transfer to system memory by DMA, interrupt, and polling

Debug support