CHAPTER 15:12-/10-/8-bit Analog to Digital Converter
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
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−
The channel is not first in the group i.e. the trigger type bits TRGTYP are set to "10" in the
corresponding ADC12Bn_CHCTRL0 to 31 register
−
The channel did not win arbitration for the next conversion, i.e. there was a channel with active
trigger status and higher priority.
For multiple conversion logical channels, this bit is set to "1" also in the case the multiple conversions
are started and they are interrupted before the last conversion is performed.
This bit is cleared by writing "1" to the corresponding ADC12Bn_GRPIRQC0 bits.
This bit is identical to the GRPIRQ bit in the corresponding ADC12Bn_CHSTAT0 to 31 registers
Summary of Contents for S6J3200 Series
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