Cypress S6J3200 Series, Manual

Page: 679 / 1355

CHAPTER 21:Ethernet MAC
678 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
4.26.
Stacked VLAN Register (ETHERNETn_stacked_vlan)
Description of Stacked VLAN register is shown.
REGISTER_NAME ETHERNETn_stacked_vlan
OFFSET 0x0C0
ACCESS_SIZE W
MULTIPLE
NUMERIC_TYPE
OTHER
BIT_OFFSET 31 30 29 28 27 26 25 24
BIT_NAME enable_processing Reserved
ACCESS_TYPE R/W R0,WX
PROT_TYPE Wp
INITIAL_VALUE 0 0x00
BIT_OFFSET 23 22 21 20 19 18 17 16
BIT_NAME Reserved
ACCESS_TYPE R0,WX
PROT_TYPE Wp
INITIAL_VALUE 0x00
BIT_OFFSET 15 14 13 12 11 10 9 8
BIT_NAME match[15:8]
ACCESS_TYPE R/W
PROT_TYPE Wp
INITIAL_VALUE 0x00
BIT_OFFSET 7 6 5 4 3 2 1 0
BIT_NAME match[7:0]
ACCESS_TYPE R/W
PROT_TYPE Wp
INITIAL_VALUE 0x00
[bit31] enable_processing: Enable processing
Enable stacked VLAN processing mode
[bit30:16] Reserved
Always read "0". Writing has no effect.
[bit15:0] match: User defined VLAN_TYPE field
When Stacked VLAN is enabled, the first VLAN tag in a received frame will only be accepted if the
VLAN type field is equal to this user defined VLAN_TYPE OR equal to the standard VLAN type
(0x8100). Note that the second VLAN tag of a Stacked VLAN packet will only be matched correctly if its
VLAN_TYPE field equals 0x8100.