Cypress S6J3200 Series, Manual

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CHAPTER 24:Inter-IC Sound (I2S)
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 945
[bit21] RBERM : Rx Block Size Error Interrupt Mask
This is interrupt mask bit of reception channel block size error.
It becomes "1" by software reset.
Bit Description
0 Interrupt to CPU by I2Sn_STATUS:RBERR is not masked
1 Interrupt to CPU by I2Sn_STATUS:RBERR is masked
[bit20] RXUDM : Rx FIFO Underflow Interrupt Mask
This is reception FIFO underflow interrupt mask bit.
It becomes "1" by software reset.
Bit Description
0 Interrupt to CPU by I2Sn_STATUS:RXUDR is not masked
1 Interrupt to CPU by I2Sn_STATUS:RXUDR is masked
[bit19] RXOVM : Rx FIFO Overflow Interrupt Mask
This is interrupt mask bit of reception FIFO overflow.
It becomes "1" by software reset.
Bit Description
0 Interrupt to CPU by I2Sn_STATUS:RXOVR is not masked
1 Interrupt to CPU by I2Sn_STATUS:RXOVR is masked
[bit18] EOPM : EOPI Interrupt Mask
This is interrupt mask bit by EOPI of status register.
It becomes "1" by software reset.
Bit Description
0 Interrupt to CPU by I2Sn_STATUS:EOPI is not masked
1 Interrupt to CPU by I2Sn_STATUS:EOPI is masked
[bit17] RXFDM : Rx FIFO DMA Mask
This is reception DMA request mask bit.
It becomes "1" by software reset.
Bit Description
0
DMA transfer is requested when reception data written to reception FIFO is more than threshold value,
previous Rx DMA block transfer has completed and there is no Rx block size error.
1 DMA transfer is not requested
[bit16] RXFIM : Rx FIFO Interrupt Mask
This is reception FIFO interrupt mask bit.
It becomes "1" by software reset.