Cypress S6J3200 Series, Manual

Page: 65 / 1355

CHAPTER 7:Memory and Base Address Map
64 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
1.
Memory Map
Memory area of not-implemented function is not supported. See the chapter of function list.
Start
Address
End
Address
Group Part
0000_0000
Internal area for CR5 Complex
TCRAM 8MB@Max
007F_FFFF Reserved
0080_0000 TCFLASH 8MB@Max
00FF_FFFF Reserved
0100_0000
AXI_FLASH 16MB@Max
01FF_FFFF
0200_0000
Shared Flash and memory area
System RAM 8MB@Max
027F_FFFF Reserved
0280_0000 0280_0FFF Exclusive Access Memory
0280_1000 03FF_FFFF Reserved
0400_0000 05FF_FFFF AXI_SLAVE_CORE0
0600_0000 07FF_FFFF Reserved
0800_0000 09FF_FFFF Reserved
0A00_0000 0BFF_FFFF Reserved
0C00_0000 0DFF_FFFF Reserved
0E00_0000 Work_FLASH 3M@Max
0E7F_FFFF Reserved
0E80_0000 0E80_1FFF
BACKUP_RAM 8K
(Backup RAM power supply domain:PD4_0)
0E80_2000 0E80_3FFF
BACKUP_RAM 8K
(Backup RAM power supply domain:PD4_1)
0E80_4000 0EFF_FFFF Reserved
0F00_0000 0FFF_FFFF Reserved
1000_0000 1FFF_FFFF
Reserved Reserved 2000_0000 2FFF_FFFF
3000_0000 3FFF_FFFF
4000_0000 4FFF_FFFF
Graphic subsystem
(AppS #8)
Memory for DDRHSSPI/Hyper Bus ch.1/ch.2
5000_0000 501F_FFFF 2MB VRAM
5020_0000 5020_03FF 2D Graphics Core Subsystem control
5020_0400 5021_0BFF 2D Graphics core(Blit,Drawing,Capture,Display,CmdSeq)
5021_0C00 5021_0FFF MPU_AXI( Capture Controller)
5021_1000 5021_13FF MPU_AXI( Blit Engine)
5021_1400 5021_17FF MPU_AXI( Drawing Engine)
5021_1800 5021_1FFF Reserved
5021_2000 5021_23FF DDRHSSPI configuration
5021_2400 5021_3FFF Reserved
5021_4000 5021_43FF Reserved
5021_4400 5021_47FF AXI Interconnect(Error Monitor)