CHAPTER 25:Programmable CRC
964
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
Table 3-3 Preliminary Checksum #1 Bit-wise and/or Byte-wise Reflection/Swapping
ROBYT
ROBIT
LEN
Preliminary Checksum #2
+3
+2
+1
+0
Action
0
0
32
S31---S24
S23---S16
S15---S8
S7---S0
No swapping/reflection. The checksum is
aligned with the polynomial degree/length.
21
0000 0000
000 S20---S16
S15---S8
S7---S0
No swapping/reflection. The checksum is
aligned with the polynomial degree/length.
The bits S21 to S31 are "0".
16
0000 0000
0000 0000
S15---S8
S7---S0
No swapping/reflection. The checksum is
aligned with the polynomial degree/length.
The bits S16 to S31 are "0".
3
0000 0000
0000 0000
0000 0000
00000
S2--S0
No swapping/reflection. The checksum is
aligned with the polynomial degree/length.
The bits S3 to S31 are "0".
1
32
S24---S31
S16---S23
S8---S15
S0---S7
Byte aligned checksum reflection.
21
0000 0000
S16---S20 000
S8---S15
S0---S7
Bit reflection. The checksum is byte
aligned. Bit S21-S23 and S24-S31 are "0".
16
0000 0000
0000 0000
S8---S15
S0---S7
Bit reflection. The checksum is byte
aligned. Bit S16-S31 are "0".
3
0000 0000
0000 0000
0000 0000
S0---S2
00000
Bit reflection. The checksum is byte
aligned. Bit S3-S7 and S8-S31 are "0".
1
0
32
S7---S0
S15---S8
S23---S16
S31---S24
Byte aligned checksum swapping.
21
0000 0000
S7---S0
S15---S8
000
S20---S16
Byte swapping. The checksum is byte
aligned. Bit S21-S23 and S24-S31 are "0".
16
0000 0000
0000 0000
S7---S0
S15---S8
Byte aligned checksum swapping. Bit
S16-S31 are "0".
3
0000 0000
0000 0000
0000 0000
00000
S2_S0
No byte swapping. Bit S3-S7 and S8-S31
are "0".
1
32
S0---S7
S8---S15
S16---S23
S24---S31
Bit reflection and byte swapping aligned
with polynomial degree/length.
21
0000 0000
000 S0---S4
S5---S12
S13---S20
Bit reflection and byte swapping. The
checksum is aligned with polynomial
length/degree. Bit S21-S23 and S24-S31
are "0".
16
0000 0000
0000 0000
S0---S7
S8---S15
Bit reflection and byte swapping. The
checksum is aligned with polynomial
length/degree. Bit S16-S31 are "0".
3
0000 0000
0000 0000
0000 0000
00000
S0---S2
Bit reflection and byte swapping. The
checksum is aligned with polynomial
length/degree. Bit S3-S7 and S8-S31 are
"0".
7. The checksum after applying settings of CRCn_CFG:ROBIT/ROBYT is "preliminary checksum #2".
8. The "preliminary checksum #2" is XOR’ed with the contents of CRCn_FXOR register to get the "final
checksum".
9. The "final checksum" gets available at CRCn_RD register.
Summary of Contents for S6J3200 Series
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