Cypress S6J3200 Series, Manual

Page: 57 / 1355

CHAPTER 5:Clock Configuration
56 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
Function Clock Name
Source Clock
System
Configuration
Sound mixer
CLK_CD5
CLK_CD5A0
CLK_CD5B0 PLL3 See Traveo Platform hardware manual
Ethernet
Media-LB
CLK_HAPP1B0 SSCG0/PLL0 See Traveo Platform hardware manual
Registers of
Indicator PWM and
LCDE
CLK_SYSC0P SSCG0/PLL0 See Traveo Platform hardware manual
FPD-LINK Converter CLK_LCP0 PPL0 or SSCG0 See Traveo Platform hardware manual
Registers of LCDC CLK_LCP1A PPL0 or SSCG0 See Traveo Platform hardware manual
Hardware watchdog
timer
CLK_HWWDT
Internal CR oscillator
(High frequency) or
Internal CR oscillator
(Low frequency)
See Traveo Platform hardware manual
Software watchdog
timer
CLK_SWWDT
Internal CR oscillator
(High frequency) or
Internal CR oscillator
(Low frequency) or
Main clock or
Sub clock
See Traveo Platform hardware manual
External interrupt
capture unit
CLK_EICU Main clock See Traveo Platform hardware manual
Real time clock CLK_RTC Main clock See Traveo Platform hardware manual
Real time clock CLK_RTC Sub clock See Traveo Platform hardware manual
Note:
−
The frequency of PLLout (output of PLL/SSCG PLL multiplier circuit) should be 800MHz or less.
−
The frequency of CLK_CPU should be 232MHz or less if its source clock is SSCG.
The relation between source clock and local clock in product-specific functions is as follows.
Table 2-2: Source Clock - Local Clock List
Source Clock
System
Clock Name Function
Local clock
name
Description
External input
clock External input
clock
Ethernet MAC TX_CLK
-
External input
clock External input
clock
Ethernet MAC RX_CLK
-
External input
clock External input
clock
Inter IC Sound (I2S0/I2S1) SCK
-
External input
clock External input
clock
Inter IC Sound (I2S0/I2S1) ECLK
-
External input
clock External input
clock
Media Local Bus Interface (MediaLB) MLBn_CLK
-