Cypress S6J3200 Series, Manual

Page: 1323 / 1355

CHAPTER 36:Appendix
1322 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
Slave Master
Group/Category Module
CPU DMAC#0 TIC DAP SHE MLB
Graphic
Subsystem
Ethernet
M M M M M M
AppS #8
Graphic subsystem
Memory for
DDRHSSPI/Hyper Bus
ch.1/ch.2
Y N
VRAM Y N
2D Graphics Core
Subsystem control
Y N
2D Graphics core
(Blit,Drawing,Capture,Displ
ay,CmdSeq)
Y N
MPU_AXI( Capture
Controller)
Y N
MPU_AXI( Blit Engine) Y N
MPU_AXI( Drawing Engine) Y N
DDRHSSPI configuration Y N
AXI Interconnect(Error
Monitor)
Y N
MPU_AXI
(3D_Graphics_Core_Write
Port A)
Y N
MPU_AXI
(3D_Graphics_Core_Write
Port B)
Y N
MPU_AXI
(3D_Graphics_Core_Write
Port C)
Y N
Hyper Bus ch.1 Control
Register
Y N
Hyper Bus ch.2 Control
Register
Y N
3D Graphics Core Y N
High Performance Bus
Matrix
Y N
AppS #11
HSSPI1_MEMORY
Memory for Hyper Bus ch.0 Y
EBI Group
Memory Y
Register p Y N
DDR-HSSPI Group
Memory Y
Register p Y N