CHAPTER 24:Inter-IC Sound (I2S)
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S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
[30] RBERR : Rx Block Size Error
When I2Sn_DMAACT:RDMACT is "1" and block transfer through DMA reception channel is more than
I2Sn_INTCNT:RFTH + 1, this bit is set to 1 and the DMA reception channel is stopped.
When RBERR is "1" and I2Sn_INTCNT:RBERM is "0", interrupt to CPU occurs.
This bit becomes "0" by software reset.
[bit29] FERR : Frame Error
Occurrence of frame error is indicated. This bit is set to "1" in the following cases:
−
Frame synchronous signal cannot be received with the set frame rate in the free-running mode
(I2Sn_CNTREG:FRUN = "0") and the slave mode (I2Sn_CNTREG:MSMD = "0").
−
The next frame synchronous signal is received during frame transmission/reception in the slave
mode (I2Sn_CNTREG:MSMD), not free-running mode (I2Sn_CNTREG:FRUN = "1").
When FERR is "1" and I2Sn_INTCNT:FERRM is "0", interrupt to CPU occurs.
Writing "1" from CPU clears the value to "0".
This bit becomes "0" by software reset.
[bit28] TXUDR1 : Tx FIFO Underflow Error
When transmission FIFO underflows at the start of frame, the value is set to "1".
When TXUDR1 is "1" and I2Sn_INTCNT:TXUD1M is "0", interrupt to the CPU occurs.
Writing "1" from CPU clears the value to "0".
This bit becomes "0" by software reset.
Note:
−
When the transmission FIFO underflows at the start of frame, there will be no more attempts to
read the transmission FIFO during the rest of the frame, so if the transmission FIFO is not written
after it has underflown, I2Sn_STATUS:TXUDR0 is not set to "1".
[bit27] TXUDR0 : Tx FIFO Underflow Error
When transmission FIFO underflows during frame transmission (from 2nd bit word to the last frame of
the word), the value is set to "1".
When TXUDR0 is "1" and I2Sn_INTCNT:TXUD0M is "0", interrupt to the CPU occurs.
Writing "1" from CPU clears the value to "0".
This bit becomes "0" by software reset.
Note:
−
When the transmission FIFO underflows during frame transmission and is still empty at the start
of the next frame, I2Sn_STATUS:TXUDR1 is set to "1" too.
[bit26] TXOVR : Tx FIFO Overflow Error
When transmission FIFO overflows, the value is set to "1" indicating transmission data is written in the
condition that transmission FIFO is full. The value "1" indicates 1 word or more of transmission data is
ignored.
When TXOVR is "1" and I2Sn_INTCNT:TXOVM is "0", interrupt to CPU occurs.
Summary of Contents for S6J3200 Series
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