Cypress S6J3200 Series, Manual

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CHAPTER 25:Programmable CRC
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 971
[bit26] CDEN : DMA Request Enable bit
This bit enables/disables the DMA request
Bit Description
0 Disable the DMA request
1 Enable the DMA request
DMA request is generated when CRC is in buffer empty state and CRCn_CFG:CDEN is set. DMA ISR
should clear this bit after final transfer. Clearing this bit by CPU at any other time might lead to
unwanted behavior.
[bit25] CIEN : CRC Interrupt Enable bit to CPU
This bit enables/disables the interrupt request.
Bit Description
0 Disable the interrupt request
1 Enable the interrupt request
The IRQ is triggered when CRCn_CFG:CIEN bit is enabled and CRC interrupt flag (CRCn_CFG:CIRQ)
is set.
[bit24] CIRQ : CRC Interrupt Flag
This bit indicates the interrupt status of CRC.
Bit Description
0
No interrupt request
Note:
CPU clears interrupt flag by writing CRCn_CFG:CIRQCLR bit to "1":
1 Interrupt request
Checksum has been calculated by CRC engine and is available in CRCn_RD register.
[bit23:22] SZ[1:0] : CRC Input Data Size Configuration bits
These bits are used to configure the input data size as follows
Bits Description
00 8-bit
01 16-bit
10 24-bit
11 32-bit
[bit21:16] LEN[5:0] : CRC Polynomial/Checksum Length Configuration bits
These bits are used to configure the length (degree) of CRC polynomial/checksum as follows:
Bits Description
100000 32
011111 31
..... .....
000010 2
Notes:
−
The following settings are not supported:
−
CRCn_CFG:LEN > 32
−
CRCn_CFG:LEN < 2