CHAPTER 23:Stereo Audio DAC
894
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
Bits
Description
00000
to
111111
This field defines the number of empty entries in the FIFO buffer, which triggers a DMA request and/or a
data request interrupt when it is exceeded..
Note:
−
FIFO buffer is 32bit * 24word. If this field is set to a value from 0 to 23, DAC_DMA_REQ and
DAC_DATA_REQ_IRQ is generated when the number of empty FIFO buffer entries exceeds this
value. If this field is set to a value greater than 23, DAC_DMA_REQ and DAC_DATA_REQ_IRQ
are never generated.
−
These bits must not be changed during the DMA transfers.
[bit15:9] Reserved
This bit is reserved.
Always write "0" to this bit. The read value is "0".
[bit8] DMAEN: DMA enable
Explanation of DMA enable
Bit
Description
0
The DMA interface is disabled (default)
1
The DMA interface is enabled
Notes:
−
This bit must not be changed during the DMA transfers
[bit7:0] Reserved
This bit is reserved.
Always write "0" to this bit. The read value is "0".
Summary of Contents for S6J3200 Series
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