Cypress S6J3200 Series, Manual

Page: 586 / 1355

CHAPTER 21:Ethernet MAC
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 585
a frame fragment might be stored in a sequence of receive buffers. Software can detect this by looking for
Start of Frame bit set in a buffer following a buffer with no End of Frame bit set.
For a properly working 10/100 MBit/s Ethernet system there should be no excessive length frames or
frames greater than 128 bytes with CRC errors. Collision fragments will be less than 128 bytes long,
therefore it will be a rare occurrence to find a frame fragment in a receive buffer, when using the value of
128 bytes for the receive buffers size (ETHERNETn_dma_config:rx_buf_size[7:0]).
When in full store and forward mode only good received frames are written out of the Ethernet MAC DMA,
so no fragments will exist in the buffers due to MAC Receiver errors. There is still the possibility of
fragments due to Ethernet MAC DMA errors, for example used bit read on the second buffer of a
multi-buffer frame.
If bit 0 of the receive buffer descriptor is already set when the receive buffer manager reads the location of
the receive buffer, then the buffer has been already used and cannot be used again until software has
processed the frame and cleared bit 0. In this case, the "buffer not available" bit in the Receive Status
register is set and an interrupt triggered. The Receive Resource Errors statistics register is also
incremented.
When the Ethernet MAC DMA is configured in the full store and forward mode, it can be selected whether
received frames should be automatically discarded when no AXI buffer resource is available. This feature
is selected via bit 24 of the DMA Configuration register (by default, the received frames are not
automatically discarded). If this feature is off, then received packets will remain to be stored in the RX
Packet Buffer Memory until system memory resource next becomes available. This may lead to an
eventual packet buffer overflow if packets continue to be received when bit 0 (“Used” bit) of the receive
buffer descriptor remains set. Note that after a “Used” bit has been read, the receive buffer manager will
re-read the location of the receive buffer descriptor every time a new packet is received. When the
Ethernet MAC DMA is not configured in the full store and forward mode and a “Used” bit is read, the
frame currently being received will be automatically discarded.
When the Ethernet MAC DMA is configured in the full store and forward mode, a receive over run
condition occurs when the RX Packet Buffer Memory is full, or because an AXI error occurred. In all other
modes, a receive over run condition occurs when either the AXI bus was not granted quickly enough, or
because an AXI error occurred, or because a new frame has been detected by the receive block when
the status update or write back for the previous frame has not yet finished. For a receive over run
condition, the receive over run interrupt is asserted and the buffer currently being written is recovered.
The next frame that is received whose address is recognized reuses the buffer.
When the Ethernet MAC DMA is configured for packet buffer mode, the upper bits of the data buffer
address stored in bits [31:2] in the first word of each list entry can be dynamically altered in real-time
without physically changing the system memory holding the list entry. This feature is useful if the
destination has to be selected based on CPU usage or other flow control hardware. It is achieved using a
MUX structure whereby it can be defined whether the upper 4 bits of the 32-bit data-buffer AXI address
should come from the descriptor list entry or from a programmable register. Refer to the Receive DMA
Data Buffer Address Mask register for further details. Note that any changes to this register will be
ignored while the Ethernet MAC DMA is currently processing a receive packet. It will only affect the next
full packet to be written to system memory.