Cypress S6J3200 Series, Manual

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CHAPTER 21:Ethernet MAC
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 685
4.32.
Receive DMA Data Buffer Address Mask Register
(ETHERNETn_dma_addr_or_mask)
Description of Receive DMA Data Buffer Address Mask register is shown.
REGISTER_NAME ETHERNETn_dma_addr_or_mask
OFFSET 0x0D0
ACCESS_SIZE W
MULTIPLE
NUMERIC_TYPE
OTHER
BIT_OFFSET 31 30 29 28 27 26 25 24
BIT_NAME mask_value[3:0] Reserved
ACCESS_TYPE R/W R0,WX
PROT_TYPE Wp
INITIAL_VALUE 0x0 0x0
BIT_OFFSET 23 22 21 20 19 18 17 16
BIT_NAME Reserved
ACCESS_TYPE R0,WX
PROT_TYPE Wp
INITIAL_VALUE 0x00
BIT_OFFSET 15 14 13 12 11 10 9 8
BIT_NAME Reserved
ACCESS_TYPE R0,WX
PROT_TYPE Wp
INITIAL_VALUE 0x00
BIT_OFFSET 7 6 5 4 3 2 1 0
BIT_NAME Reserved mask_enable[3:0]
ACCESS_TYPE R0,WX R/W
PROT_TYPE Wp
INITIAL_VALUE 0x0 0x0
[bit31:28] mask_value: Data Buffer Address Mask Value
Values used to force bits [31:28] of the receive data buffer AXI address to a particular value when the
associated enable bits stored in this register [3:0] are set. Any changes to this register will be ignored
while the DMA is currently processing a receive packet. It will only affect the next full packet to be
written to system memory.
[bit27:4] Reserved
Always read "0". Writing has no effect.