Cypress S6J3200 Series, Manual

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CHAPTER 31:Memory Protection Unit for AXI
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 1149
4.2.
MPU AXI NMI Enable Register (MPUXn_NMIEN)
MPU AXI NMI Enable Register can be used by software to reset NMI enable bit. Default value of NMI
enable bit is "1". This bit can be reset by software only once after reset operation.
 MPUXn_NMIEN
MPUXn_NMIEN
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0
N
MI
E
N
R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0
R
W
P
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bit Position Bit Field Name Bit Description
[31:8] read0
-
[7:1] read0
-
[0] NMIEN
NMI Interrupt Enable
This bit decides whether the NMI interrupt flag is routed to NMI interrupt
signal or not.
"0": NMI interrupt flag does not trigger NMI interrupt signal "1": NMI interrupt
flag triggers NMI interrupt signal
The value of this bit can be changed only once after reset.