Cypress S6J3200 Series, Manual

Page: 621 / 1355

CHAPTER 21:Ethernet MAC
620 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
[bit25] pfc_ctrl: PFC control
Enable multiple PFC pause quanta, one per pause priority
Bit Description
0 Disable
1 Enable
[bit24] one_step_sync_mode: IEEE 1588 Timer One Step Sync Mode
Replace timestamp field in the IEEE 1588 header for TX Sync Frames with current IEEE 1588 Timer
value.
Bit Description
0 Disable
1 Enable
[bit23] Reserved
Always read "0". Writing has no effect.
[bit22] store_udp_offset: Store UDP/TCP Offset
Store UDP/TCP offset to memory.
Bit Description
0 Normal operation.
1
The upper 16-bits of the CRC of every received frame are replaced with the offset from start of frame to
the beginning of the UDP or TCP header. The lower 16-bits of the CRC are replaced with zero and
reserved for future use.
[bit21] Reserved
Always read write value. Always write “0”.
[bit20] ptp_unicast_ena: PTP Unicast Frames Enable
Enable the detection of PTP unicast frames.
Bit Description
0 Disable
1 Enable
[bit19] tx_lpi_en: LPI Transmission Enable
Enable immediate transmission of LPI (low power idle).
Bit Description
0 Disable
1 Enable
[bit18] flush_rx_pkt_clk: Flush Next Packet From External RX DPRAM
Bit Description
0 No effect
1
Writing this bit to "1" will only have an effect if the DMA is currently not reading a packet stored in RX
DPRAM to memory.