Cypress S6J3200 Series, Manual

Page: 370 / 1355

CHAPTER 15:12-/10-/8-bit Analog to Digital Converter
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 369
5.34.
A/D Multiple Conversion Channel Control Registers
(ADC12Bn_MCCTRL0 to 3)
These registers ADC12Bn_MCCTRL0 to 3 contain additional configuration bits for the first four logical
channels (multiple conversion logical channels). They control number of conversions, multiple conversion
interrupt and A/D Converter calibration setup. Only ADC12Bn_MCCTRL0 is described here. Other
registers (ADC12Bn_MCCTRL1, ADC12Bn_MCCTRL2 and ADC12Bn_MCCTRL3) have identical bit
fields.
REGISTER_NAME ADC12Bn_MCCTRLi (i = 0 to 3)
OFFSET i
ACCESS_SIZE B H W
MULTIPLE 0:3
NUMERIC_TYPE
-
OTHER
-
A/D Multiple Conversion Channel Control Register (ADC12Bn_MCCTRL0)
BIT_OFFSET 7 6 5 4 3 2 1 0
BIT_NAME Reserved AVRHSEL AVRLSEL ICIRQY CNVNUM[3] CNVNUM[2] CNVNUM[1] CNVNUM[0]
ACCESS_TYPE R0,W0 R/W R/W R/W R/W R/W R/W R/W
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
[bit7] Reserved : Reserved bit
When writing, always write "0".
When reading, "0" is always read.
[bit6] AVRHSEL : A/D reference voltage AVRH selection bit
Bit Description
0 AVRH voltage is not selected for A/D conversion
1 AVRH voltage is selected for A/D conversion.
In case that both bits AVRHSEL and AVRLSEL bits are set to "1", AVRLSEL has higher priority and
AVRL voltage is converted.
If any of AVRHSEL/ARVRLSEL bits is set to "1", conversion of a regular analog input AN is not
possible.
For further explanation of A/D Converter calibration refer to section "A/D Converter Calibration" in
chapter "3 Operation of A/D ".
[bit5] AVRLSEL : A/D reference voltage AVRL selection bit
Bit Description
0 AVRL voltage is not selected for A/D conversion
1 AVRL voltage is selected for A/D conversion