Cypress S6J3200 Series, Manual

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Table of Contents
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 13
4.96. PTP Event Frame Received Nanoseconds Register
(ETHERNETn_tsu_ptp_rx_nsec).......................................................................... 753
4.97. PTP Peer Event Frame Transmitted Seconds [31:0] Register
(ETHERNETn_tsu_peer_tx_sec).......................................................................... 754
4.98. PTP Peer Event Frame Transmitted Nanoseconds Register
(ETHERNETn_tsu_peer_tx_nsec)........................................................................ 755
4.99. PTP Peer Event Frame Received Seconds [31:0] Register
(ETHERNETn_tsu_peer_rx_sec) ......................................................................... 756
4.100. PTP Peer Event Frame Received Nanoseconds Register
(ETHERNETn_tsu_peer_rx_nsec) ....................................................................... 757
4.101. Transmit Pause Quantum 1 Register (ETHERNETn_tx_pause_quantum1) ......... 758
4.102. Transmit Pause Quantum 2 Register (ETHERNETn_tx_pause_quantum2) ......... 759
4.103. Transmit Pause Quantum 3 Register (ETHERNETn_tx_pause_quantum3) ......... 760
4.104. Receive LPI Transitions Register (ETHERNETn_rx_lpi) ...................................... 761
4.105. Received LPI Time Register (ETHERNETn_rx_lpi_time) ..................................... 762
4.106. Transmit LPI Transitions Register (ETHERNETn_tx_lpi) ...................................... 763
4.107. Transmit LPI Time Register (ETHERNETn_tx_lpi_time)....................................... 764
4.108. Design Configuration 3 Register (ETHERNETn_designcfg_debug3) ................... 765
4.109. Design Configuration 4 Register (ETHERNETn_designcfg_debug4) ................... 766
4.110. Design Configuration 5 Register (ETHERNETn_designcfg_debug5) ................... 767
4.111. Design Configuration 6 Register (ETHERNETn_designcfg_debug6) ................... 769
4.112. Design Configuration 7 Register (ETHERNETn_designcfg_debug7) ................... 772
4.113. Design Configuration 8 Register (ETHERNETn_designcfg_debug8) ................... 774
4.114. Design Configuration 9 Register (ETHERNETn_designcfg_debug9) ................... 776
4.115. Design Configuration 10 Register (ETHERNETn_designcfg_debug10) ............... 778
4.116. Interrupt Status Queue i Register (ETHERNETn_int_status_qi) (i=1 to 3) ........... 780
4.117. TX Buffer Queue 1 Base Address Register (ETHERNETn_transmit_q1_ptr) ....... 782
4.118. TX Buffer Queue 2 Base Address Register (ETHERNETn_transmit_q2_ptr) ....... 784
4.119. TX Buffer Queue 3 Base Address Register (ETHERNETn_transmit_q3_ptr) ....... 786
4.120. RX Buffer Queue 1 Base Address Register (ETHERNETn_receive_q1_ptr) ........ 788
4.121. RX Buffer Queue 2 Base Address Register (ETHERNETn_receive_q2_ptr) ........ 790
4.122. RX Buffer Queue 3 Base Address Register (ETHERNETn_receive_q3_ptr) ........ 792
4.123. RX Buffer Size Queue i Register (ETHERNETn_rxbuf_size_qi) (i=1 to 3) ........... 794
4.124. CBS Control Register (ETHERNETn_cbs_control) .............................................. 796
4.125. CBS IdleSlope Queue A Register (ETHERNETn_cbs_idleslope_q_a) ................. 798
4.126. CBS IdleSlope Queue B Register (ETHERNETn_cbs_idleslope_q_b) ................. 799
4.127. MSB Buffer Queue Base Address Register
(ETHERNETn_msb_buff_q_base_addr_reg) ....................................................... 800
4.128. TX BD Control Register (ETHERNETn_tx_bd_control) ........................................ 801
4.129. RX BD Control Register (ETHERNETn_rx_bd_control) ....................................... 803
4.130. Screening Type 1 Register i (ETHERNETn_screening_type_1_register_i) (i=0 to
15) ........................................................................................................................ 805
4.131. Screening Type 2 Register i (ETHERNETn_screening_type_2_register_i) (i=0 to
15) ........................................................................................................................ 807
4.132. Interrupt Enable Queue i Register (ETHERNETn_int_enable_qi) (i=1 to 3) ......... 809
4.133. Interrupt Disable Queue i Register (ETHERNETn_int_disable_qi) (i=1 to 3) ........ 811
4.134. Interrupt Mask Queue i Register (ETHERNETn_int_mask_qi) (i=1 to 3) .............. 813