Cypress S6J3200 Series, Manual

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CHAPTER 24:Inter-IC Sound (I2S)
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 943
4.9.
Interrupt Control Register (I2Sn_INTCNT)
This register is to enable or disable interrupt function.
Interrupt Control Register (I2Sn_INTCNT)
BIT_OFFSET 31 30 29 28 27 26 25 24
BIT_NAME read0 TXUD1M TBERM FERRM TXUD0M TXOVM TXFDM TXFIM
ACCESS_TYPE R0,WX R/W R/W R/W R/W R/W R/W R/W
PROT_TYPE
INITIAL_VALUE 0 1 1 1 1 1 1 1
BIT_OFFSET 23 22 21 20 19 18 17 16
BIT_NAME read0 read0 RBERM RXUDM RXOVM EOPM RXFDM RXFIM
ACCESS_TYPE R0,WX R0,WX R/W R/W R/W R/W R/W R/W
PROT_TYPE
INITIAL_VALUE 0 0 1 1 1 1 1 1
BIT_OFFSET 15 14 13 12 11 10 9 8
BIT_NAME read0 read0 read0 read0 TFTH[3] TFTH[2] TFTH[1] TFTH[0]
ACCESS_TYPE R0,WX R0,WX R0,WX R0,WX R/W R/W R/W R/W
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 7 6 5 4 3 2 1 0
BIT_NAME read0 read0 RPTMR[1] RPTMR[0] RFTH[3] RFTH[2] RFTH[1] RFTH[0]
ACCESS_TYPE R0,WX R0,WX R/W R/W R/W R/W R/W R/W
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
[bit31] read0 : -
[bit30] TXUD1M : Tx FIFO Underflow Interrupt Mask
This is transmission FIFO underflow interrupt mask bit.
It becomes "1" by software reset.
Bit Description
0 Interrupt to CPU by I2Sn_STATUS:TXUDR1 is not masked
1 Interrupt to CPU by I2Sn_STATUS:TXUDR1 is masked
[bit29] TBERM : Tx Block Size Error Interrupt Mask
This is interrupt mask bit of block size error of transmission channel.
It becomes "1" by software reset.