Cypress S6J3200 Series, Manual

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CHAPTER 3:Product Description
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 41
Feature Description
Internal Memories
TCRAM
See the platform manual in detail.
Internal Memories
Backup RAM
16KBytes
Backup RAM can only be operated in RUN mode (normal operation mode). In other mode the memory
content should be retained, but it cannot be operated. SLEEP control for Buckup RAM is not supported
and cannot be used.
Internal Memories
VRAM
ECC region is shared with user region.
Memory size available for user program become less when ECC is enabled.
User can define ECC enabled area and ECC disabled area.
Single error correction, double error detection (SECDED) ECC support per 32-bit word.
Embedded
Program/Work Flash Memory
Embedded Program Flash can be accessed with 0-wait-cycle if CPU frequency is 80MHz or less.
0-wait-cycle: 80MHz or less.
1-wait-cycle: 160MHz or less.
2-wait-cycle: more than 160MHz.
The maximum frequency should be referred in datasheet.
Erase suspend is supported. Reading and writing to the other sector are possible when Flash Erase is
suspended.
Serial Flash programing and Parallel Flash programing are supported.
Margin mode is not supported.
Security
Chip erase function is available for flash memory.
The function of "MK_CEER" is not supported. (MK_CEER = not selectable)
For details, see the platform manual and chapter "Security"
Internal Power Domain
PD1: Always ON
PD2: Cortex R5F platform/ GDC/ additional peripherals
PD4: Backup RAM in Always On domain
PD6: Peripherals in Always On domain
* The chapter of the block diagram explains in detail.
Power Supply
External 5V, 3V, 1.2V is required.
Built in LDO provides internal 1.2V for Always On region (PD1).
External 1.2V power supply control pin is supported.
External 3.3V power supply should be controlled by GPIO.
There are constraints of power on/off sequence.
Low-voltage Detection
LVD for external voltage is supported.
LVD for internal voltage is supported.
See the specification of the detected level on the datasheet.
Low-voltage Detection for
RAM Retention (RVD) RVD for RAM retention is effective during the standby mode only. That is, it is only for the Backup RAM of
16KB that the function is available.
Resource inter-connect The output signal of some resources can be inputted to the other resource.
I/O Ports
5V general purpose I/O
3V general purpose I/O
Multi input level and multi output drivability
Pull-up, pull-down function is available.
Resource input and output is multiplexed.
+B input is allowed many pins of 3.3V, 5V and 3.3V/5V I/O domain.